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n1506hkim 20060911-s00002 no.a0548-1/21 ver.1.00 lc863g64a,lc863g56a lc863g48a,LC863G40A lc863g32a,lc863g28a lc863g24a overview the lc863g64a/56a/48a/40a/32a/28a/24a are 8-bit single chip microcontrollers with the following on-chip functional blocks: ? cpu: operable at a minimu m bus cycle time of 0.424s ? on-chip rom capacity program rom: 64k/56k/48k/40k/32k/28k/24k bytes cgrom: 16k bytes ? on-chip ram capacity: 768 bytes ? osd ram: 352 9 bits ? closed-caption tv controller and the on-screen display controller ? closed-caption data slicer ? four channels 8-bit ad converter ? three channels 7-bit pwm ? two 16-bit timer/counters, 14-bit base timer ? 8-bit synchronous seri al interface circuit ? iic-bus compliant serial interface circuit (multi-master type) ? uart interface circuit (full duplex) ? rom correction function ? 18-source 10-vectored interrupt system ? integrated system clock generator and display clock generator only one x?tal oscillator (32.768khz) for p ll reference is used for both generators tv control and the closed caption function all of the above functions are fabricated on a single chip. ordering number : ena0548 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before usingany sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. cmos ic 64k/56k/48k/40k/32k/28k/24k-byte rom, cgrom16k-byte on-chip 768-byte ram and 352 9 bit osd ram 8-bit 1-chip microcontroller trademarks iic is a trademark of phili p s cor p oration. n ote : this product includes the iic bus inte rface circuit. if you intend to use the iic bus interface, pleas e notify us of thi s in advance of our receiving your program rom code order. purchase of sanyo iic components conveys a license under the philips iic patents rights to use these components in an iic system, provided that the sy stem conforms to the iic standard specification as defined by philips.
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-2/21 features ? read-only memory (rom): 65536 8 bits/57344 8 bits/49152 8 bits/ 40960 8 bits/32768 8 bits/28672 8 bits/24576 8 bits for program 16128 8 bits for cgrom ? random access memory (ram): 768 8 bits (including 128 bytes for rom correction function) 352 9 bits (for crt display) ? osd functions ? screen display : 36 characters 16 lines (by software) ? ram : 352 words (9 bits per word) display area : 36 words 8 lines control area : 8 words 8 lines ? characters up to 252 kinds of 16 32 dot character fonts (4 characters includi ng 1 test character are not programmable) each font can be divided into two parts and used as two fonts: a 16 17 dot and 8 9 dot character font at least 111 characters need to be divide to display the caption fonts. ? various character attributes character colors : 16 colors character background colors : 16 colors fringe/shadow colors : 16 colors full screen colors : 16 colors rounding underline italic character (slanting) ? attribute can be changed without spacing ? vertical display start line number can be set for each row independently (rows can be overlapped) ? horizontal display start position can be set for each row independently ? horizontal pitch (9 to 16 dots) *1 and vertical pitch (1 to 32 dots) can be set for each row independently ? different display modes can be set for each row independently caption ? text mode/osd mode 1/osd mode 2 (quarter size) /simplified graphic mode ? ten character sizes *1 horiz. vert. = (1 1), (1 2), (2 2), (2 4), (0.5 0.5) (1.5 1), (1.5 2), (3 2), (3 4), (0.75 0.5) ? shuttering and sc rolling on each row ? simplified graphic display ? external osd clock input enable note *1: range depends on display mode: refer to manual for details. ? data slicer (closed caption format) ? closed caption data and xds data extraction ? ntsc/pal, and extracted line can be specified ? bus cycle time / instruction-cycle time bus cycle time instruction cycle ti me clock divider system clock osci llation oscillation frequency voltage 0.424s 0.848s 1/2 internal vco (ref: x?tal 32.768khz) 14.156mhz 4.5v to 5.5v 7.5s 15.0s 1/2 internal rc 800khz 4.5v to 5.5v 91.55s 183.1s 1/1 crystal 32.768khz 4.5v to 5.5v 183.1s 366.2s 1/2 crystal 32.768khz 4.5v to 5.5v
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-3/21 ? ports ? input / output ports : 5 ports (28 terminals) data direction programmable in nibble units : 1 port (8 terminals) (if the n-ch open drain output is selected by option, the corresponding port data can be read in output mode.) data direction programmable for each bit individually : 4 ports (20 terminals) ? ad converter ? 4-channels 8-bit ad converters ? serial interfaces ? iic-bus compliant serial interface (multi-master type) consists of a single built-in circuit with two i/o channels . the two data lines and two clock lines can be connected internally. ? synchronous 8-bit serial interface ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit ? built-in baudrate generator ? pwm output ? 3 channels 7-bit pwm ? timer ? timer 0: 16-bit timer/counter with 2-bit prescaler + 8-b it programmable prescaler mode 0: two 8-bit timers with a programmable prescaler mode 1: 8-bit timer with a programmable prescaler + 8-bit counter mode 2: 16-bit timer with a programmable prescaler mode 3: 16-bit counter the resolution of timer is 1 tcyc. ? timer 1: 16-bit timer/pwm mode 0: two 8-bit timers mode 1: 8-bit timer + 8-bit pwm mode 2: 16-bit timer mode 3: variable bit pwm (9 to 16 bits) in mode 0/1, the resolution of timer1/pwm is 1 tcyc in mode 2/3, the resolution is selectable by program; tcyc or 1/2 tcyc ? base timer generate every 500ms overflow for a clock application (using 32.768khz crystal oscillation for the base timer clock) generate every 976s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768khz crystal oscillation for the base timer clock) clock for the base timer is selectable from 32.768khz cr ystal oscillation, system clock or programmable prescaler output of timer 0 ? remote control receiver circuit (conne cted to the p73/in t3/t0in terminal) ? noise rejection function ? polarity switching ? watchdog timer external rc circuit is required interrupt or system reset is activated when the timer overflows ? rom correction function max 128 bytes/2 addresses
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-4/21 ? interrupts ? 18 source 10 vectored interrupts 1. external interrupt int0 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8 bits) 6. timer t1h, t1l 7. sio0, uart receive 8. data slicer, uart transmit 9. vertical synchronous signal interrupt ( vs ), horizontal line ( hs ), ad 10. iic, port 0 ? interrupt priority control three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. low or high priority can be assigned to the interrupts from 3 to 10 listed above. for the external interrupt int0 and int1 , low or highest priority can be set. ? sub-routine stack level ? a maximum of 128 levels (stack is built in the internal ram) ? multiplication/division instruction ? 16 bits 8 bits (7 instruction cycle times) ? 16 bits 8 bits (7 instruction cycle times) ? 3 oscillation circuits ? built-in rc oscillation circuit used for the system clock ? built-in vco circuit used for the system clock and osd ? x?tal oscillation circuit used for base timer, system clock and pll reference ? standby function ? halt mode the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this mode can be released by the interrupt request or the system reset. ? hold mode the hold mode is used to stop the oscillations; rc (internal), vco and x?tal oscillations. this mode can be released by the following conditions. - pull the reset terminal ( res ) to low level. - feed the selected level to either p70/int0 or p71/int1. - input the interrupt condition to port 0. ? package ? dip42s(600mil): lead-free type ? qip48e(14 14) : lead-free type ? development tools ? flash eeprom: lc86f3g64a ? emulator: special rom monitor tool (when debugging it, one terminal in the i/o port is used as a pin only for the tool)
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-5/21 package dimensions unit : mm (typ) 3025c package dimensions unit : mm (typ) 3156a sanyo : dip42s(600mil) 37.7 13.8 0.95 0.48 (1.05) 1.78 (4.25) 3.8 5.1max 0.51min 15.24 0.25 121 42 22 sanyo : qip48e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 1.0 (1.5) 1 12 13 24 25 36 37 48 (2.7) 3.0max 0.1
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-6/21 pin assignments sanyo: dip42s(600mil) ?lead-free type? sanyo: qip48e(14 14) ?lead-free type? top view p10/so0 p11/si0 p12/sck0 p13/pwm1 p14/pwm2/t x p15/pwm3/r x p16/osdc k p17/pwm v ss xt1 xt2 v dd p84/an4 p85/an5 p86/an6 p87/an7 res filt cvin vs hs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p07 p06 p05 p04 p03 p02 p01 p00 p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 i bl b g r lc863g64a lc863g56a lc863g48a LC863G40A lc863g32a lc863g28a lc863g24a p02 p01 p00 nc p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 nc p14/pwm2/tx p13/pwm1 p12/sck0 p11/si0 p10/so0 nc p07 p06 p05 p04 p03 res filt cvin nc vs hs r g b bl i nc p15/pwm3/rx p16/osdc k p17/pwm v ss xt1 xt2 v dd nc p84/an4 p85/an5 p86/an6 p87/an7 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 top view lc863g64a lc863g56a lc863g48a LC863G40A lc863g32a lc863g28a lc863g24a
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-7/21 system block diagram interrupt control standby control clock generator x?tal vco rc pll ir pla rom pc acc b register c register alu psw rar ram stack pointer port 0 watch dog timer rom correct control xram bus interface port 1 port 6 port 7 port 8 osd control circuit vram cgrom iic sio0 timer 0 timer 1 base timer adc int0-3 noise rejection filter pwm data slicer uart
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-8/21 pin description pin description table terminal i/o function description option v ss - negative power supply xt1 i input terminal for crystal oscillator xt2 o output terminal for crystal oscillator v dd - positive power supply res i reset terminal filt o filter terminal for pll cvin i video signal input terminal vs i vertical synchronization signal input terminal hs i horizontal synchronization signal input terminal r o red (r) output terminal of rgb image output g o green (g) output terminal of rgb image output b o blue (b) output terminal of rgb image output i o intensity ( i ) output terminal of rgb image output bl o fast blanking control signal switch tv image signal and caption/osd image signal port 0 p00 to p07 i/o ?8-bit input/output port, input/output can be specified in nibble unit ?other functions hold release input interrupt input pull-up register provided/not provided output format cmos/nch-od port 1 ?8-bit input/output port input/output can be specified in a bit ?other functions output format cmos/nch-od p10 p11 p12 p13 p14 p15 p16 p17 sio0 data output sio0 data input/bus input/output sio0 clock input/output pwm1 output pwm2 output/uart transmit pwm3 output/uart receive external osd clock input timer1 (pwm) output p10 to p17 i/o port 6 ?4-bit input/output port input/output can be specified for each bit ?other functions p60 p61 p62 p63 iic0 data i/o iic0 clock output iic1 data i/o iic1 clock output p60 to p63 i/o continued on next page.
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-9/21 continued from preceding page. terminal i/o function description option port 7 ?4-bit input/output port input or output can be specified for each bit ?other function p70 p71 p72 p73 int0 input/hold release input/ nch-tr. output for watchdog timer int1 input/hold release input int2 input/timer 0 event input int3 input (noise rejection filter connected)/ timer 0 event input interrupt receiver format, vector addresses rising falling rising/ falling h level l level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h p70 p71 to p73 i/o int3 enable enable enable disable disable 1bh port 8 p84 to p87 i/o ?4-bit input/output port input or output can be specified for each bit ?other function ad converter input port (4 lines) nc - unused terminal leave open ? output form and existence of pull-up resistor for all ports can be specified for each bit. ? programmable pull-up resistor is always connected regardless of port option, cmos or n-ch open drain output in port 1. ? port status in reset terminal i/o pull-up resistor status at selecting pull-up option port 0 i pull-up resistor off, on after reset release port 1 i programmable pull-up resistor off
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-10/21 absolute maximum ratings at ta = 25c, v ss = 0v specification parameter symbol pins conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd -0.3 +6.5 input voltage v i (1) ? res , hs , vs , cvin -0.3 v dd +0.3 output voltage v o (1) r, g, b, i, bl, filt -0.3 v dd +0.3 input/output voltage v io ? ports 0, 1, 6, 7, 8 -0.3 v dd +0.3 v ioph(1) ? ports 0, 1, 7, 8 ? cmos output ? for each pin. -4 peak output current ioph(2) r, g, b, i, bl ? cmos output ? for each pin. -5 ioah(1) ? ports 0, 1 the total of all pins. -20 ioah(2) ports 7, 8 the total of all pins. -10 high level output current total output current ioah(3) r, g, b, i, bl the total of all pins. -15 iopl(1) ports 0, 1, 6, 8 for each pin. 15 iopl(2) port 7 for each pin. 15 peak output current iopl(3) r, g, b, i, bl for each pin. 5 ioal(1) ports 0, 1 the total of all pins. 40 ioal(2) ports 6, 7, 8 the total of all pins. 35 low level output current total output current ioal(3) r, g, b, i, bl the total of all pins. 15 ma dip42s(600mil) 520 maximum power dissipation pd max qip48e(14 14) ta=-10 to +70 c 280 mw operating temperature range topr -10 +70 storage temperature range tstg -55 +125 c
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-11/21 recommended operating range at ta = -10c to +70c, v ss = 0v specification parameter symbol pins conditions v dd [v] min typ max unit v dd (1) 0.844s tcyc 0.852s 4.5 5.5 operating supply voltage range v dd (2) v dd 4s tcyc 400s 4.5 5.5 hold voltage vhd v dd rams and the registers data are kept in hold mode. 2.0 5.5 v ih (1) port 0 (schumitt) output disable 4.5 to 5.5 0.6v dd v dd v ih (2) ? ports 1,6 (schumitt cmos ) ? port 7 (schumitt) port input/interrupt ? hs , vs , res (schumitt) output disable 4.5 to 5.5 0.75v dd v dd v ih (3) port 70 watchdog timer input output disable 4.5 to 5.5 v dd -0.5 v dd v ih (4) ? port 8 port input output disable 4.5 to 5.5 0.7v dd v dd high level input voltage v ih (5) ? port 16 (ttl) ? port 6 (schumitt ttl) port input output disable 4.5 to 5.5 0.45v dd v dd v il (1) port 0 (schumitt) output disable 4.5 to 5.5 v ss 0.2v dd v il (2) ? ports 1,6 (schumitt cmos ) ? port 7 (schumitt) port input/interrupt ? hs , vs , res (schumitt) output disable 4.5 to 5.5 v ss 0.25v dd v il (3) port 70 watchdog timer input output disable 4.5 to 5.5 v ss 0.6v dd v il (4) port 8 port input output disable 4.5 to 5.5 v ss 0.3v dd v low level input voltage v il (5) ? port 16 (ttl) ? port 6 (schumitt ttl) port input output disable 4.5 to 5.5 v ss 0.18v dd cvin vcvin cvin 5.0 1vp-p -3db 1vp-p 1vp-p +3db vp-p* tcyc(1) ? all functions operating 4.5 to 5.5 0.844 0.848 0.852 tcyc(2) ? ad converter operating ? osd and data slicer are not operating 4.5 to 5.5 0.844 30 operation cycle time tcyc(3) ? osd, ad converter and data slicer are not operating 4.5 to 5.5 0.844 400 s oscillation frequency range fmrc internal rc oscillation 4.5 to 5.5 0.4 0.8 3.0 external osd clock input frequency range fmick p16/osdck duty50 5% of external osd clock 4.5 to 5.5 13 14 15 mhz * vp-p: peak-to-peak voltage
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-12/21 electrical characteristics at ta = -10c to +70c, v ss = 0v specification parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 6, 7, 8 ? output disable ? pull-up mos tr. off ? v in =v dd (including the off-leak current of the output tr.) 4.5 to 5.5 1 high level input current i ih (2) ? res ? hs , vs ? v in =v dd 4.5 to 5.5 1 i il (1) ports 0, 1, 6, 7, 8 ? output disable ? pull-up mos tr. off ? v in =v ss (including the off-leak current of the output tr.) 4.5 to 5.5 -1 low level input current i il (2) ? res ? hs , vs v in =v ss 4.5 to 5.5 -1 a v oh (1) ?cmos output of ports 0, 1, 71 to 73, 8 i oh =-1.0ma 4.5 to 5.5 v dd -1 high level output voltage v oh (2) r, g, b, i, bl i oh =-0.1ma 4.5 to 5.5 v dd -0.5 v ol (1) ports 0, 1, 71 to 73, 8 i ol =10ma 4.5 to 5.5 1.5 v ol (2) ports 0, 1, 71 to 73, 8 i ol =1.6ma 4.5 to 5.5 0.4 v ol (3) ? r, g, b, i, bl ? port 6 i ol =3.0ma 4.5 to 5.5 0.4 v ol (4) port 6 i ol =6.0ma 4.5 to 5.5 0.6 low level output voltage v ol (5) port 70 i ol =1ma 4.5 to 5.5 0.4 v pull-up mos tr. resistance rpu ? ports 0, 1, 7, 8 v oh =0.9v dd 4.5 to 5.5 13 38 80 k ? bus terminal short circuit resistance (scl0 to scl1, sda0 to sda1) rbs ? p60 to p62 ? p61 to p63 4.5 to 5.5 130 300 ? hysteresis voltage vhys ? ports 0, 1, 6, 7 ? res ? hs , vs output disable 4.5 to 5.5 0.1v dd input clump voltage vclmp cvin 5.0 2.3 2.5 2.7 v pin capacitance cp all pins ? f=1mhz ? every other terminals are connected to v ss . ? ta=25 c 4.5 to 5.5 10 pf
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-13/21 serial input/output characteristics at ta = -10c to +70c, v ss = 0v specification parameter symbol pins conditions v dd [v] min typ max unit cycle tckcy(1) 2 low level pulse width tckl(1) 1 input clock high level pulse width tckh(1) ? sck0 ? sclk0 refer to figure 4. 4.5 to 5.5 1 cycle tckcy(2) 2 low level pulse width tckl(2) 1/2tckcy serial clock output clock high level pulse width tckh(2) ? sck0 ? sclk0 ? use pull-up resistor (1k ? ) when nch open-drain output. ? refer to figure 4. 4.5 to 5.5 1/2tckcy tcyc data set up time tick 0.1 serial input data hold time tcki si0 ? data set-up to sck0. ? data hold from sck0. ? refer to figure 4. 4.5 to 5.5 0.1 output delay time (using external clock) tcko(1) so0 4.5 to 5.5 7/12tcyc +0.2 serial output output delay time (using internal clock) tcko(2) so0 ? data hold from sck0. ? use pull-up resistor (1k ? ) when nch open-drain output. ? refer to figure 4. 4.5 to 5.5 1/3tcyc +0.2 s iic input/output conditions at ta = -10c to +70c, v ss = 0v standard high speed parameter symbol min max min max unit scl frequency fscl 0 100 0 400 khz bus free time between stop to start tbuf 4.7 1.3 s hold time of start, rest art condition thd; sta 4.0 0.6 s l time of scl tlow 4.7 1.3 s h time of scl thigh 4.0 0.6 s set-up time of restart condition tsu; sta 4.7 0.6 s hold time of sda thd; dat 0 0 0.9 s set-up time of sda tsu; dat 250 100 ns rising time of sda, scl tr 1000 20+0.1cb 300 ns falling time of sda, scl tf 300 20+0.1cb 300 ns set-up time of stop condition tsu; sto 4.0 0.6 s refer to figure 10 note 1: cb: total capacitance of all bus (unit: pf)
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-14/21 uart (full duplex) op erating conditions at ta = -10c to +70c, v ss = 0v specification parameter symbol pin/remarks condition v dd [v] min typ max unit ubr(1) transfer rate* ubr(2) p14, 15 0.844 s tcyc 400 s 4.5 to 5.5 16/6 8192/6 tcyc * high speed mode: ubr= (n+1) (8/6)tcyc low speed mode: ubr= (n+1) (32/6)tcyc n=1 to 255 data length :7/8/9 bits(lsb first) stop bits :1 bit parity bits :none example of continuous 8-bit data transmission mode processing (first transmit data = 55h) example of continuous 8-bit da ta reception mode processing (first receive data = 55h) ubr start of reception start bit stop bit receive data (lsb first) end of reception ubr start of transmission start bit stop bit transmit data (lsb first) end of transmission
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-15/21 pulse input conditions at ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) ? int0, int1 ? int2/t0in ? interrupt acceptable ? timer0-countable 4.5 to 5.5 1 tpih(2) tpil(2) int3/t0in (1tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer0-countable 4.5 to 5.5 2 tpih(3) tpil(3) int3/t0in (16tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer0-countable 4.5 to 5.5 32 tpih(4) tpil(4) int3/t0in (64tcyc is selected for noise rejection clock.) ? interrupt acceptable ? timer0-countable 4.5 to 5.5 128 tcyc tpil(5) res reset acceptable 4.5 to 5.5 200 high/low level pulse width tpih(6) tpil(6) hs , vs ? display position controllable ? the active edge of hs and vs must be apart at least 1 tcyc. ? refer to figure 6. 4.5 to 5.5 3 s rising/falling time tthl ttlh hs refer to figure 6. 4.5 to 5.5 500 ns external osd clock input tosck osdck (p16) refer to figure 7. 4.5 to 5.5 10 ns ad converter characteristics at ta = -10c to +70c, v ss = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 8 bit absolute precision et (note 2) 1.5 lsb adcr2=0 (note 3) 16 conversion time tcad adcr2=1 (note 3) 32 tcyc analog input voltage range vain v ss v dd v iainh vain=v dd 1 analog port input current iainl an4 to an7 vain=v ss 4.5 to 5.5 -1 a note 2: absolute precision does not include quantizing error (1/2lsb). note 3: conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent.
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-16/21 sample current dissipation characteristics at ta = -10c to +70c, v ss = 0v the sample current dissipation characteristics is the measurement result of sanyo provided evaluation board when the recommended circuit parameters shown in the sample os cillation circuit characteristics are used externally. the currents through the output transistors and the pull-up mos transistors are ignored. limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) ?fmx?tal=32.768khz x?tal oscillation ?system clock: vco ?vco for osd operating ?internal rc oscillation stops 4.5 to 5.5 10 24 ma current dissipation during basic operation (note 4) iddop(2) ?fmx?tal=32.768khz x?tal oscillation ?system clock: x'tal (instruction cycle time: 366.2 s) ?vco for system, vco for osd, internal rc oscillation stop ?data slicer, ad converters stop 4.5 to 5.5 55 300 a iddhalt(1) ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?system clock: vco ?vco for osd stops ? internal rc oscillation stops 4.5 to 5.5 3 9 ma iddhalt(2) ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?vco for system stops ?vco for osd stops ?system clock: internal rc 4.5 to 5.5 300 1000 current dissipation in halt mode (note 4) iddhalt(3) ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?vco for system stops ?vco for osd stops ?system clock: x?tal (instruction cycle time: 366.2 s) 4.5 to 5.5 45 200 a current dissipation in hold mode (note 4) iddhold v dd ?hold mode ?all oscillation stops. 4.5 to 5.5 0.05 20 a note 4: the currents through the output transistors and the pull-up mos transistors are ignored.
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-17/21 recommended oscillation circui t and sample characteristics the sample oscillation circuit characteristics in the table below is based on the following conditions: ? recommended circuit parameters are verified by an os cillator manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluatio n with the recommended circuit parameters connected externally. recommended oscillation circuit and sample characteristics (ta = -10c to +70c) recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rf rd operating supply voltage range typ max notes 32.768khz seiko epson c-002rx 18pf 18pf open 390k ? 4.5 to 5.5v 1.0s 1.5s notes: the oscillation stabilizing time period is the time un til the vco oscillation for the internal system becomes stable after the following conditions . (refer to figure 2) 1. the v dd becomes higher than the minimum operating voltage after the power is supplied. 2. the hold mode is released. the sample oscillation circuit characteristics may differ ap plications. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of th e application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and the operating supply vo ltage range are based on the operating temperature of -10c to +70c. for the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. ? when using the oscillator which is not shown in the samp le oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by th e noise or wiring capacity becau se the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (xt1 terminal xt2 terminal) and external parts should be as short as possible. ? the capacitors? v ss should be allocated close to the microcontroller?s gnd terminal and be away from other gnd. ? the signal lines with rapid state changes or with large cu rrent should be allocated away from the oscillation circuit. figure 1 recommended oscillation circuit c1 rd c2 x?tal xt2 xt1 rf
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-18/21 figure 2 oscillation stabilizing time power supply res internal rc resonato r oscillation xt1,xt2 vco for system operation mode reset time v dd v dd limit 0v unfixed instruction execution mode reset tmsvco stable tmsvco stable valid instruction execution mode hold hold release xt1, xt2 vco for system operation mode internal rc resonato r oscillation
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-19/21 figure 3 reset circuit figure 4 serial input/output test condition figure 5 pulse input timing condition -1 (note) determine the c res , r res value to generate more than 200s reset time. c res v dd r res res 0.5v dd so0 sb0 si0 sck0 50pf v dd t cko t cki t ick t ckh t ckl t ckcy tpih (1) to (4) tpil (1) yo (5) 1k ?
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-20/21 figure 6 pulse input timing condition - 2 note: tosck must be saving constant figure 7 pulse input timing condition - 3 figure 8 recommended interface circuit output impedance of c-video before noise filter should be less then 100 ? . figure 9 cvin recommended circuit lc863g64a hs 10k ? ?
lc863g64a/56a/48a/ 40a/32a/28a/24a no.a0548-21/21 note: place filt parts on board as clos e to the microcontroller as possible. figure 10 filt recommended circuit s : start condition tsp : spike suppression standard mode : not exist p : stop condition high speed mode : less than 50ns sr : restart condition figure 11 iic timing ps filt 100 ? ? 2.2 s sr p tbuf thd;sta tr tlow thd;dat thigh tf tsu;dat tsu;sta thd;sta tsp tsu;sto this catalog provides information as of november, 2006. specifications and information herein are subject to change without notice. specifications of any and all sanyo semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high- quality high-reliability products. however, any and all semiconductor products fail with some probabi lity. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. sanyo semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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